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-- Company: 
-- Engineer:
--
-- Create Date:   10:53:52 09/18/2013
-- Design Name:   
-- Module Name:   C:/Xilinx/Projects/Lab2/test_ALU.vhd
-- Project Name:  Lab2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ALU
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY test_ALU IS
END test_ALU;
 
ARCHITECTURE behavior OF test_ALU IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ALU
    PORT(
         ALU_Operand1 : IN  std_logic_vector(31 downto 0);
         ALU_Operand2 : IN  std_logic_vector(31 downto 0);
         ALU_Control : IN  std_logic_vector(5 downto 0);
         CLK : IN  std_logic;
         ALU_Result1 : OUT  std_logic_vector(31 downto 0);
         ALU_Result2 : OUT  std_logic_vector(31 downto 0);
         ALU_Debug : INOUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal ALU_Operand1 : std_logic_vector(31 downto 0) := (others => '0');
   signal ALU_Operand2 : std_logic_vector(31 downto 0) := (others => '0');
   signal ALU_Control : std_logic_vector(5 downto 0) := (others => '0');
   signal CLK : std_logic := '0';

	--BiDirs
   signal ALU_Debug : std_logic_vector(31 downto 0);

 	--Outputs
   signal ALU_Result1 : std_logic_vector(31 downto 0);
   signal ALU_Result2 : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ALU PORT MAP (
          ALU_Operand1 => ALU_Operand1,
          ALU_Operand2 => ALU_Operand2,
          ALU_Control => ALU_Control,
          CLK => CLK,
          ALU_Result1 => ALU_Result1,
          ALU_Result2 => ALU_Result2,
          ALU_Debug => ALU_Debug
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for CLK_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
